---
title: "Qwenputer Compiles a RISC-V CPU Into Model Weights, With a Large Practical Cost"
description: "An experimental Qwen3.5-4B derivative embeds an exact RISC-V processor in constructed neural layers and uses recurrent state as RAM. The design is inspectable, but not a replacement for ordinary tools."
date: 2026-11-04
topic: open-source
tags: ["qwenputer","qwen","open-weights","risc-v","gated-deltanet","neural-computation"]
production: ai-assisted
source: https://notes.suffro.com/posts/qwenputer-riscv-cpu-inside-model-weights-2026-11-04
---

# Qwenputer Compiles a RISC-V CPU Into Model Weights, With a Large Practical Cost

A language model can generate a plausible answer to an arithmetic question without actually performing the calculation. The usual engineering answer is to let it call a calculator or execute code in a separate environment. [Qwenputer](https://github.com/divagr18/qwenputer), an experimental project by Divyansh Agrawal published in October 2026, asks a different question: can the computation itself be encoded in the model's neural-network layers, with no separately invoked calculator?

The published answer is a modified Qwen3.5-4B checkpoint containing a 32-bit RISC-V processor. Its instructions are implemented by weights calculated by a compiler, not by gradient descent. The model's recurrent Gated DeltaNet state holds the processor's memory. Code, an architectural description, test programs and checkpoints are public. This is a substantial technical experiment, not a claim that neural inference has become a sensible replacement for conventional CPUs.

## A processor built from layers, not learned behavior

The [RV32 design document](https://github.com/divagr18/qwenputer/blob/main/experimental/riscv/docs/rv32.md) describes an eleven-layer processor circuit placed ahead of Qwen3.5-4B's existing 32 layers. The implementation uses standard attention and feed-forward components, with a circuit compiler assigning their weights. It implements the RV32IM instruction set, the Zba address-generation extension and custom operations for long integer arithmetic.

The author reports 42,012 MLP units, 99 attention heads and about 1.04 million nonzero circuit weights in the standalone processor design. Those figures should not be confused with the storage cost of the merged checkpoint. Standard dense tensor layouts require padding and widened dimensions; the merged model is approximately 18.7 GB in BF16 according to the project's technical documentation.

The more unusual component is memory. In the [Gated DeltaNet explanation](https://github.com/divagr18/qwenputer#​​gated-deltanet-as-ram), a recurrent state matrix can be addressed with one-hot keys and queries. Holding the gate and write strength at one allows an update to replace a selected row while leaving the other rows unchanged. A corresponding query reads that row. By assigning heads and rows to addresses, the circuit stores RAM, registers, the program counter and other machine state inside the network's recurrence.

This is deterministic, engineered state manipulation rather than an emergent ability learned from examples. It also illustrates why the distinction between model weights and runtime state matters: the processor's logic is in the weights, but its changing memory contents live in the recurrent state.

## What happens when Qwen asks for a calculation

Qwenputer uses Qwen's existing tool-call syntax as an interface. The model can emit a call for `calc`, but an external calculator is not registered to execute it. The added layers recognize the relevant tokens, run the firmware inside the constructed processor and emit the answer as tokens the language-model layers can read.

There is still a host program. The [quickstart](https://github.com/divagr18/qwenputer#quickstart) uses an `RvChat` driver to load firmware into recurrent state, manage the execution trace and coordinate decoding. The distinction is not that computation happens without hardware, a runtime or supporting software. It is that the arithmetic instruction semantics are implemented by the model's constructed layers rather than by an external tool service. The project's faster path uses a Triton executor to evaluate the same circuit.

The [repository](https://github.com/divagr18/qwenputer) contains the compiler and processor implementation under `experimental/riscv/`, reference-machine checks, tests and firmware. Its Python package specifies dependencies including NumPy and safetensors, with PyTorch and Transformers in the optional Hugging Face environment. The model checkpoint is [distributed separately](https://huggingface.co/divagr1925/Qwen3.5-4B-Qwenputer). This is inspectable source and a downloadable artifact, not merely a demonstration video.

## Exact machine execution is not the same as exact answers

The developer reports that the processor passes the official RISC-V instruction tests and agrees with QEMU on a collection of compiled programs. The [technical measurements](https://github.com/divagr18/qwenputer/blob/main/experimental/riscv/docs/rv32.md) also describe reference replay of circuit-owned output positions, with no mismatches in the reported checks. These are author-run results, not independent reproductions conducted for this article.

The arithmetic evaluation is particularly revealing. The [README benchmark table](https://github.com/divagr18/qwenputer#benchmarks) uses greedy decoding with 40 problems per set and compares the original Qwen3.5-4B, Qwenputer and the original model given a host Python tool. On DeepMind's `mul_big` set, the reported accuracies are 55%, 97.5% and 100%, respectively. On `div_big`, they are 72.5%, 97.5% and 95%. On a longer mixed multiplication/division set, Qwenputer and the host-tool baseline also score highly.

That is evidence of a useful computational mechanism, but it does not show that the full language-model interaction is mathematically infallible. The processor can return the correct result and Qwen can still mishandle the answer, make repeated calls or exhaust its generation budget. The [RV32 report](https://github.com/divagr18/qwenputer/blob/main/experimental/riscv/docs/rv32.md) documents these failure modes explicitly, including a case where a correct fraction was returned but the model's final answer differed. The author subsequently changed the calculator firmware to support exact rational arithmetic across intermediate operations, improving the difficult mixed-expression results.

The small evaluation sets and development-specific decoding paths matter. Some comparisons use different batch settings and hardware paths. The evidence supports the existence of the implemented processor and the reported test results, not a general claim of superior mathematical reasoning.

## Why the cost changes the interpretation

The circuit is slow relative to a real CPU. The project's [RV32 documentation](https://github.com/divagr18/qwenputer/blob/main/experimental/riscv/docs/rv32.md) reports approximately 3,200 circuit trace tokens per second on an NVIDIA L4 with the optimized executor, compared with about 250 on the Hugging Face module path. An arithmetic request may consume thousands of trace tokens. The document reports approximately half a second to one second for a calculator call on the optimized path, while full model reasoning can take substantially longer.

A host calculator performs ordinary arithmetic with negligible compute overhead by comparison. Qwenputer's advantage is therefore not lower latency or cheaper execution. It demonstrates that exact algorithmic computation can be embedded into the same general neural primitives used by a pretrained model, without changing the original language-model weights through training.

The project also explores a filesystem stored in recurrent state and an experimental neural-processing extension. The [README](https://github.com/divagr18/qwenputer#in-weight-filesystem-experimental) explicitly labels these as work in progress, with code on separate branches and separate checkpoints. They should not be treated as completed capabilities of the main RISC-V release. State persistence requires saving and restoring the relevant runtime state; it does not make a file survive automatically just because the checkpoint exists.

## An open experiment with clear boundaries

The repository's [LICENSE](https://github.com/divagr18/qwenputer/blob/main/LICENSE) grants the code an MIT license, with an explicit exception for bundled CHIP-8 game ROMs. The author identifies the modified model weights as Apache-2.0, inherited from the [Qwen3.5-4B base checkpoint](https://huggingface.co/Qwen/Qwen3.5-4B). Code and weights have distinct licenses, and the experimental additions do not make all bundled assets MIT-licensed.

The most interesting implication is architectural. Recurrent state can be deliberately organized as addressable memory, while hand-constructed neural layers can implement exact symbolic operations. That provides a concrete counterexample to the assumption that every capability inside a model must be acquired by training. It also raises useful questions about verification and visibility: what parts of a model's state are observable, which operations can be checked against a reference machine, and how much complexity is justified by keeping computation inside inference?

For production systems, external calculators and isolated code execution remain simpler and much more efficient. For researchers studying hybrid neural-symbolic computation, Qwenputer offers something more valuable than a benchmark headline: a source-visible construction, an explicit instruction set and a set of reported checks that others can attempt to reproduce. No independent execution or benchmark reproduction was performed for this article.

## Sources

- [Divyansh Agrawal, Qwenputer source repository, implementation, README and benchmarks](https://github.com/divagr18/qwenputer)
- [Qwenputer RV32 technical design, validation records and performance measurements](https://github.com/divagr18/qwenputer/blob/main/experimental/riscv/docs/rv32.md)
- [Qwenputer code license and bundled ROM exception](https://github.com/divagr18/qwenputer/blob/main/LICENSE)
- [Qwenputer RISC-V checkpoint and model files on Hugging Face](https://huggingface.co/divagr1925/Qwen3.5-4B-Qwenputer)
- [Qwen3.5-4B base checkpoint and license](https://huggingface.co/Qwen/Qwen3.5-4B)
- [Divyansh Agrawal, Qwenputer essay series (October 22, 2026)](https://divagr.com/series/qwenputer)
- [NYU Shanghai RITS, independent technical overview (October 29, 2026)](https://rits.shanghai.nyu.edu/ai/qwenputer-runs-a-risc-v-cpu-inside-qwens-own-weights/)